The present invention relates to a dynamic RAM (Random Accesss Memory) and a semiconductor integrated circuit and to a technology for valid use in a memory access technique for accessing dynamic memory cells.
A dynamic RAM is known in which a back bias voltage to be supplied to a substrate and a boosted select voltage for selecting a word line are formed by a voltage generator using a built-in charge pump circuit.
The use of an external supply voltage for the voltage as selecting a word line or lowering a unselect voltage for not selecting a word line is described in Japanese Patent Laid-Open Nos. Hei 2-5290, Hei 5-89673, Hei 6-215566, Hei 6-215572, and Hei 5-12866.
A dynamic memory cell consists of an address select MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and an information storage capacitor. An information storage operation is performed whether this capacitor is charged or not. To extend the formation retention time in the charged state, it is required to supply a negative back bias voltage to a substrate gate (a channel section) on which the address select MOSFET is formed to raise its effective threshold voltage. In a MOSFET constituting a peripheral circuit for address-selecting the above-mentioned dynamic memory cell and a sense amplifier and main amplifier, when a negative back bias voltage is applied to the substrate gate, the threshold voltage increases by that amount and the conductance in the on state decreases, slowing the operation speed. To solve this problem, a method has been proposed in which such a back bias voltage is supplied only to the memory array section on which the dynamic memory cell is formed. However, such a constitution requires that the well region on which the memory array section is formed be separated from the well region on which the above-mentioned peripheral circuit is formed, making the fabrication process complicated.
In writing at high level to the dynamic memory cell, the information storage capacitor is charged up via the address selecting MOSFET, and the charge-up level is lowered by an amount equivalent to the threshold voltage of the address select MOSFET, thereby reducing the amount of the information charge. To prevent the charge-up level from being lowered, the select level of the word line connected to the gate of the above-mentioned address select MOSFET is set to a voltage boosted by a threshold voltage for the high level to be transmitted to a bit line. Thus, prior-art dynamic RAMs require a boosted voltage for a word line selecting operation and a charge pump circuit for forming the above-mentioned back bias voltage, thereby causing problems, such as a comparatively large occupancy area and increased current consumption.